1. Technical Field
Embodiments relate to a semiconductor integrated circuit, and more particularly, to a data output circuit of a semiconductor memory apparatus.
2. Related Art
In general, a semiconductor memory apparatus is configured to receive data from a pad (i.e., from the outside) and store the data therein, and configured to output the stored data to the pad (i.e., to the outside). Specifically, when the semiconductor memory apparatus receives data from the pad and stores the data therein, the semiconductor memory apparatus receives data in serial (hereinafter, referred to as ‘serial data’) and transforms the serial data to data in parallel (hereinafter, referred to as ‘parallel data’) to store the parallel data therein, and when the semiconductor memory apparatus outputs the stored data to the pad, the semiconductor memory apparatus transforms the stored parallel data to serial data to output the serial data to the pad.
FIG. 1 is a block diagram showing a configuration of a data output circuit of a conventional semiconductor memory apparatus.
FIG. 1 shows a configuration that the conventional semiconductor memory apparatus transforms stored parallel data to serial data to output the serial data to the pad. As shown in FIG. 1, the conventional semiconductor memory apparatus includes a parallel-to-serial data transform unit 10, a data driver 20, a DLL clock control unit 30, a clock synchronization unit 40, and a data output unit 50.
The parallel-to-serial data transform unit 10 receives parallel data ‘DATA_P<0:n>’ outputted from a memory cell array (not shown) to generate rising data ‘RDO’ and falling data ‘FDO’ in serial, in response to a control signal ‘ctrl’.
The data driver 20 drives the rising data ‘RDO’ and the falling data ‘FDO’ to output the driven data as driving rising data ‘RDOD’ and driving falling data ‘FDOD’, respectively.
The DLL clock control unit 30 drives a rising clock ‘RCLK’ and a falling clock ‘FCLK’, which are outputted from a DLL circuit (not shown), to output the driven clock as a driving rising clock ‘RCLKD’ and a driving falling clock ‘FCLKD’, respectively, based on an enable signal ‘en’.
The clock synchronization unit 40 synchronizes the driving rising data ‘RDOD’ and the driving falling data ‘FDOD’ with the driving rising clock ‘RCLKD’ and the driving falling clock ‘FCLKD’, respectively, to output serial rising data ‘RDATA_S’ and serial falling data ‘FDATA_S’, in a normal operation (i.e., not in a test operation). In addition, the clock synchronization unit 40 generates the serial rising data ‘RDATA_S’ and the serial falling data ‘FDATA_S’ in response to level data signal ‘LEVEL_DATA’, in the test operation (i.e., in a case where an output level test signal ‘Test_DQSLEV’ is enabled).
The data output unit 50 generates output data ‘DQ’ in response to the serial rising data ‘RDATA_S’ and the serial falling data ‘FDATA_S’. At this time, the output data ‘DQ’ are data which will be outputted to the outside of the semiconductor memory apparatus.
FIG. 2 is a diagram showing a configuration of the clock synchronization unit 40 of FIG. 1.
As shown in FIG. 2, the clock synchronization unit 40 includes a serial rising data generating unit 41 and a serial falling data generating unit 42.
The serial rising data generating unit 41 includes first to third data synchronization units 41-1, 41-2, and 41-3.
The first data synchronization unit 41-1 includes first to fourth transistors P1, P2, N1, and N2, and a first inverter IV1.
The second data synchronization unit 41-2 includes fifth to eighth transistors P3, P4, N3, and N4, and a second inverter IV2.
The third data synchronization unit 41-3 includes ninth to twelfth transistors P5, P6, N5, and N6, and a third inverter IV3. Herein, the serial rising data ‘RDATA_S’ are outputted through a fourth inverter IV4 coupled to a node to which respective output terminals of the first to third data synchronization units 41-1, 41-2, and 41-3 are commonly coupled.
Like the serial rising data generating unit 41, the serial falling data generating unit 42 includes fourth to sixth data synchronization units 42-1, 42-2, and 42-3.
The fourth data synchronization unit 42-1 includes thirteenth to sixteenth transistors P7, P8, N7, and N8, and a fifth inverter IV5.
The fifth data synchronization unit 42-2 includes seventeenth to twentieth transistors P9, P10, N9, and N10, and a sixth inverter IV6.
The sixth data synchronization unit 42-3 includes twenty-first to twenty-fourth transistors P11, P12, N11, and N12, and a seventh inverter IV7. Herein, the serial falling data ‘FDATA_S’ are outputted through an eighth inverter IV8 coupled to a node to which respective output terminals of the fourth to sixth data synchronization units 42-1, 42-2, and 42-3 are commonly coupled.
In such a configuration, the clock synchronization unit 40 makes it difficult to realize a high-speed operation and a low power consumption of the semiconductor memory apparatus.
As shown in FIG. 2, the serial rising data generating unit 41 includes a node to which the respective output terminals of the first to third data synchronization units 41-1, 41-2, and 41-3 are commonly coupled. Therefore, in order to drive a node outputting the serial rising data ‘RDATA_S’, an amount of a current consumed in the respective data synchronization units 41-1, 41-2, and 41-3 should be increased. Otherwise, if the amount of the current consumed in the respective data synchronization units 41-1, 41-2, and 41-3 is not increased, a transition time of the serial rising data ‘RDATA_S’ which the serial rising data generating unit 41 outputs is increased, thereby it is difficult for the semiconductor memory apparatus to output the output data ‘DQ’ in a high speed.
Since the serial falling data generating unit 42 has substantially the same configuration as the serial rising data generating unit 41, an amount of a current consumed in the respective data synchronization units 42-1, 42-2, and 42-3 should be increased in order to drive a node to which the respective output terminals of the fourth to sixth data synchronization units 42-1, 42-2, and 42-3 are commonly coupled. Otherwise, if the amount of the current consumed in the respective data synchronization units 42-1, 42-2, and 42-3 is not increased, a transition time of the serial falling data ‘FDATA_S’ which the serial falling data generating unit 42 outputs is increased, thereby it is also difficult for the semiconductor memory apparatus to output the output data ‘DQ’ in a high speed.